Phase change random access memory (PCRAM) is a non-volatile form of memory that uses the reversible process of changing the state of an alloy containing one or more elements from Group V or VI of the periodic table between amorphous and crystalline states upon application of an electric current, and wherein the two states have substantially different electrical resistance. Typical current phase change memories use a chalcogenide alloy, such as a Germanium-Antimony-Tellurium (GeSbTe, or GST, most commonly Ge2Sb2Te5) alloy. The amorphous (a-GST) and crystalline (c-GST) states of the material have largely different resistivity, on the order of three orders of magnitude, so that a determination of the state is easily done. The crystalline state has typical resistance on the order of kiloOhms (kΩ), whereas the amorphous state has typical resistance on the order of megaOhms (MΩ). The states are stable under normal conditions, so the PCRAM cell is a non-volatile cell with a long data retention. When the GST is in its amorphous state, it is said to be RESET. When the GST is in its crystalline state, it is said to be SET. A PCRAM cell is read by measuring its resistance.
The structure of a typical vertical PCRAM cell in a SET state 100 as shown in FIG. 1 includes a bottom metal contact 102, a bottom electrode 104 surrounded by dielectric material 106, a chalcogenide (GST) 108 having a crystalline portion (c-GST) 112, a top electrode 114, a metal top contact 116, and a cell select line 118. The GST 108 being all c-GST means that the GST has a high conductivity, and low resistance, typically on the order of kΩ. The bottom electrode 104 is sometimes referred to as a heater.
A RESET structure of the PCRAM cell 100 is shown in FIG. 2. The bottom electrode 104 is typically a high conductivity, low resistivity metal or alloy (less than 1 milliOhms·cm (mΩ·cm)). To change the cell 100 from a SET state to a RESET state, a current is passed through the bottom metal contact 102 and bottom electrode 104. This current heats a programmable volume region of the GST 108 near the top of the bottom electrode 104 to a temperature sufficient to melt the GST in that region. Typical melting points for many GST materials are in the range of 600 degrees C., although the melting point differs for other chalcogenides. When the current is removed, a section of the programmable volume of GST 108 that has been heated to its melting point rapidly cools due to heat dissipation into the surrounding materials. This rapid cooling does not allow the melted programmable volume region to cool in a crystalline state. Instead, a region of amorphous GST (a-GST 110) remains at or near the top of the heater 104.
The desired a-GST region is a hemispherical region covering the top of the bottom electrode 104 and extending slightly into the field of c-GST. This allows for a high resistance of the GST 108, as the resistances of the c-GST 112 and a-GST 110 portions behave electrically as series a connected resistance. This is shown in FIG. 3.
The majority of the heat generated by the current passing through the bottom electrode 104 does not contribute to heating of the GST 108, since the heat is dissipated by the surrounding dielectric material 106. Therefore, most of the heating of the programmable volume region of GST 108 is due to resistive heating near the top of the heater 106.
In typical PCRAM cells, the cell (the GST layer) and the top electrode are patterned together with the current flowing from the top electrode contact to the bottom electrode. In this arrangement, current density is mostly symmetric. In an ideal RESET state, a hemispheric region of GST covering the entire area of the bottom electrode contact is converted to the amorphous state (a-GST 110), to prevent a parallel leakage path.
The hottest region in the GST programmable volume is typically about 20 nanometers above the interface between the bottom electrode 104 and the GST 108 due to heat loss through bottom electrode 104. The inefficient heating of low resistance bottom electrodes 104 combined with the hottest region being above the interface between the bottom electrode 104 and the GST 108 can create an amorphous GST region that is separated from the bottom electrode as shown in FIG. 4. This leads to a parallel resistance connection for the a-GST and c-GST regions, and the current flows through the low resistance path of the parallel circuit, the result being that the cell is stuck at a low resistance state and the GST cannot be converted back to a high resistance state.
Still further, a RESET current pulse that is too large will form an ideal hemispherical amorphous region covering the bottom electrode 104, but will create a region of the GST that is too hot, often in excess of 900 degrees C. This hot spot can cause bubbling, sublimation, or composition change.
To switch the cell 100 from a RESET state to a SET state, a SET current is passed through the metal contact 102 and bottom electrode 104 to heat the a-GST section 110 near the top of the bottom electrode 104 to a temperature below the melting point, but sufficiently high (on the order of 350 degrees C. for typical GST materials, but different for other chalcogenides) at which the mobility of atoms in the region near the top of the bottom electrode 104 allows them to rearrange from an amorphous state to a crystalline state. The resulting configuration has a GST 108 that is all crystalline, as is shown in FIG. 1.
The currents used to SET and RESET the cell are typically as follows. A SET state is achieved by applying a voltage or current pulse sufficient to raise the GST temperature in the programmable volume to below the melting point but above its crystallization temperature, and is held for a sufficient time to allow the rearranging of the atoms to a crystalline state. A RESET state is achieved by applying a voltage or current pulse sufficient to raise the GST temperature in the programmable volume to the melting point, and is held typically for a shorter time than the SET pulse. The SET pulse is typically longer in duration but of lower amplitude than the RESET pulse. The RESET pulse is typically shorter in duration but of higher amplitude than the SET pulse. The actual amplitudes and durations of the pulses depend upon the size of the cells and the particular phase change materials used in the cell. RESET currents for many GST cells are currently in the 400 to 600 microAmpere (μA) range, and have durations in the 10-50 nanosecond range, whereas SET currents are currently in the 100 to 200 μA range and have durations in the 50-100 nanosecond range. Read currents are lower than either SET or RESET currents. As cell size continues to decrease, the currents involved and the durations thereof also continue to decrease.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for improved PCRAM structures and methods for phase change memory switching.